4 Bit Computer in Verilog [SAP]
- Instruction Set:
- Add A, B
- Sub A, B
- XCHG B, A
- mov B, [address]
- out B
- jnz Address
- RCR A
- mov B, BYTE
- jmp Address
- push A
- pop A
- CALL Addr
- RET
- xor A, [Addr]
- test B, BYTE
- HLT
This computer is designed in such a fashion so that all the instructions are executed sequentially.
The instruction pointer for the next instruction is passed at the end of each instruction.
Implementation Codes Available Here.